AI hardware infrastructure startup.

• Work on accelerator architecture and performance, including hardware/software co-design.
• Analyze and validate accelerator hardware rooflines for real kernel workloads; identify and resolve bottlenecks through hardware or software solutions to achieve roofline performance.
• Collaborate with the kernel and compiler teams across all layers of the software stack to connect workload behavior with architectural decisions.

Responsibilities include:

• IOMMU: Designed and implemented performance-critical IOMMU datapaths in SystemVerilog to support high-throughput DMA/RDMA flows
• Enabled high-performance interfaces: Enabled PCIe, UALink, and Infinity Fabric (IFOE) interfaces for hardware-accelerated I/O.
• Performance: Conducted architecture-level performance studies using in-house simulators and correlated results with RTL behavior
• Architecture: Contributed to cache and memory-system design discussions through documentation and analysis of state-of-the-art approaches
• Mentorship: Mentored incoming engineers, accelerating onboarding and ramp-up

Responsibilities include:

• Worked with the interconnect team at AMD on low-power, high-bandwidth interconnect logic
• Implemented and delivered 2 features in System Verilog from Architecture design documents
• Scripted for automating synthesis and testing processes, using Tcl, Bash, and Perl etc.